Scaling of memory, such as dynamic random-access memory (DRAM), is challenging in part due to lithography constraints. For example, DRAM memory cells may include an access transistor and a capacitor. As those memory cells are more aggressively scaled, it becomes increasingly difficult for circuit designers to formulate memory arrays where operating one memory cell avoids undesirable interference with an adjacent memory cell. Such interference can result in, for example, the loss of data stored within the adjacent memory cell. To prevent this interference, the adjacent memory cells may be separated from each other using insulation techniques (e.g., shallow trench isolation (STI)). However, accurate location of such insulation materials between tightly spaced adjacent memory cells is increasingly difficult as scaling increases.